1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a technique for suppressing a leakage current in a semiconductor integrated circuit. Japanese Patent Application No. 2006-277591 also relates to the semiconductor integrated circuit. The disclosure of this application is incorporated herein by reference.
2. Description of Related Art
A problem of increase in leakage current becomes important with advancement of a technique for miniaturization of a semiconductor device. The leakage current flowing unnecessarily occupies a larger portion of a total of power consumption of the semiconductor device. In order to suppress the increasing of this power consumption, various techniques are proposed in Japanese Laid Open Patent Application (JP-P2004-186666A).
FIG. 1 is a circuit diagram showing a configuration of a semiconductor device 100 described in JP-P2004-186666A. The semiconductor device 100 is related to an MT-CMOS (Multi Threshold CMOS). Referring to FIG. 1, in the semiconductor device 100, an N-channel transistor Q1 with a high threshold voltage is arranged between a higher side power supply line Vdd and a pseudo higher side power supply line Vddv. A power source terminal of a load circuit 101 is connected to the pseudo higher side power supply line Vddv and includes N-channel transistors (Q4 and Q5) with a low threshold voltage and P-channel transistors (Q2 and Q3) with a low threshold voltage.
In this way, by controlling a signal PCNT supplied to a gate of the N-channel transistor Q1 with a high threshold voltage, a leakage current of the load circuit 101 is reduced. In this technique, the load circuit 101 is provided in a specific area (for example, a functional block), and a power source for the load circuit 101 is supplied. As described above, the technique is known, in which a switch is arranged between the specific area and the power supply line to control the supply of the power when s supply of the power and blockage of the supply of the power to a certain specific area are switched.
In case of mixed existence of an area for which power supply can be blocked off (hereinafter, to be referred to as a blockade-possible area) and an area for which power is constantly supplied (hereinafter, to be referred to as an always-operating area), it is preferable that respective areas are laid out independently. However, since presently widespread semiconductor integrated circuit usually have complexities in configuration and operation, a layout of independent allocation of the blockade-possible area and the always-operating area is very difficult. For example, there is often a case that the constant operation area must be allocated in the blockade-possible area. In this case, the power supply line for the constant operation area is required to be achieved via an upper layer of the blockade-possible area. As a result, since the configuration of the semiconductor integrated circuit is complicated due to a multi-layer structure, so that manufacturing costs and working steps thereof will be increased.